This invention relates to the design of application-specific integrated circuits (“ASICs”). More particularly, the invention relates to the design of ASICs of the type known as structured ASICs that are intended to be functionally equivalent to a field-programmable gate array (“FPGA”) that has been programmed in a particular way.
FPGAs are relatively general-purpose integrated circuit devices that can be programmed to perform any of many different functions such as logic. After a design has been implemented and proven in an FPGA, it may be desirable to migrate that design to a structured ASIC. A structured ASIC is an integrated circuit that always has the same basic structure, but that has several layers that can be customized to cause the structured ASIC to implement particular functions. For example, many of the masks used to make a particular type of structured ASIC are the same or substantially the same for all ASIC products of that type. A few of the masks can be customized to give any one of those products a particular set of functions. These functions can be those that have been proven to work in a programmed FPGA. Using a structured ASIC to replicate an FPGA in this way (as opposed to attempting to design an unstructured ASIC, completely “from scratch”, for this purpose) has a number of advantages. These include faster design turn-around, lower design cost, less risk that the ASIC design will not be a good functional equivalent of the FPGA design, etc.
References such as the following show examples of structured ASICs and methods for converting FPGA designs to structured ASIC implementations of those designs: Foo U.S. patent application Ser. No. 10/861,585, filed Jun. 4, 2004; Chua et al. U.S. patent application Ser. No. 10/884,460, filed Jul. 2, 2004; Yuan et al. U.S. patent application Ser. No. 10/916,305, filed Aug. 11, 2004; Schleicher et al. U.S. patent application Ser. No. 11/050,607, filed Feb. 3, 2005; Pedersen et al. U.S. patent application Ser. No. 11/072,560, filed Mar. 3, 2005; Schleicher et al. U.S. patent application Ser. No. 11/097,633, filed Apr. 1, 2005; Yuan et al. U.S. patent application Ser. No. 11/101,949, filed Apr. 8, 2005; Park et al. U.S. patent application Ser. No. 11/108,370, filed Apr. 18, 2005; Park et al. U.S. patent application Ser. No. 11/115,641, filed Apr. 27, 2005; Lim et al. U.S. patent application Ser. No. 11/141,867, filed May 31, 2005; and Tan et al. U.S. patent application Ser. No. 11/141,941, filed May 31, 2005. (All of these references are assigned to the same assignee as this disclosure, and references identified as patent applications are co-pending with this disclosure.) As at least some of these references show, programmed-FPGA-to-structured-ASIC conversion methods frequently include use of libraries of structured ASIC cells that are known to be equivalent to particular programmed FPGA functions or cells.
There are several respects in which the known methods of converting an FPGA design to a functionally equivalent structured ASIC design could be improved. For example, the known methods do not attempt to permute the inputs to structured ASIC library cells to try to achieve better timing performance. Nor do the known methods attempt to decompose a structured ASIC library cell for similar purposes. Still another possible deficiency of known programmed-FPGA-to-structured-ASIC conversion methods is that the known methods tend to implement all adders in the structured ASIC using two-bit adder cells. These may be more costly (e.g., in terms of area occupied and power consumed) than is warranted in all cases.